Powerpc Vea Instructions; Processor Control Instructions-Vea - Motorola MPC750 User Manual

Table 2-50. Memory Synchronization Instructions-UISA (Continued)
Name
Mnemonic Syntax Implementation Notes
Synchronize sync
-
Because it delays subsequent instructions until all previous instructions
complete to where they cannot cause an exception, sync is a barrier against
store gathering. Additionally, all load/store cache/bus activities initiated by prior
instructions are completed. Touch load operations (debt, debtst) must
complete address translation, but need not complete on the bus. If HIDO[ABE]
= 1, syne completes after a successful broadcast.
The latency of sync depends on the processor state when it is dispatched and
on various system-level situations. Therefore, frequent use of syne may
degrade performance.
System designs with an L2 cache should take special care to recognize the hardware
signaling caused by a SYNC bus operation and perform the appropriate actions to
guarantee that memory references that may be queued internally to the L2 cache have been
performed globally.
See 2.3.5.2, "Memory Synchronization Instructions-VEA," for details about additional
memory synchronization (eieio and isync) instructions.
In the PowerPC architecture, the Rc bit must be zero for most load and store instructions.
If Rc is set, the instruction form is invalid for sync and lwarx instructions. If the MPC750
encounters one of these invalid instruction forms, it sets CRO to an undefined value.
2.3.5 PowerPC VEA Instructions
The PowerPC virtual environment architecture (VEA) describes the semantics of the
memory model that can be assumed by software processes, and includes descriptions of the
cache model, cache control instructions, address aliasing, and other related issues.
Implementations that conform to the VEA also adhere to the UISA, but may not necessarily
adhere to the OEA.
This section describes additional instructions that are provided by the VEA.
2.3.5.1 Processor Control Instructions-VEA
In addition to the move to condition register instructions (specified by the UISA), the VEA
defines the mftb instruction (user-level instruction) for reading the contents of the time base
register; see Chapter 3, "Ll Instruction and Data Cache Operation," for more information.
Table 2-51 shows the mftb instruction.
Table 2-51. Move from Time Base Instruction
Name Mnemonic Syntax
Move from Time Base mftb rD, TBR
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MPC750 RISC Microprocessor User's Manual