Organization Of Data In Memory - Motorola MC68030 User Manual

privilege level. All operations to the status register and CCR are word-sized
operations, but for all CCR operations, the upper byte is read as all zeros and
is ignored when written, regardless of privilege level.
The supervisor programming model (see Figure 1-3) shows the control reg-
isters. The cache control register (CACR) provides control and status infor-
mation forthe on-chip instruction and data caches. The cache address register
(CAAR) contains the address for cache control functions. The vector base
register (VBR) provides the base address of the exception vector table. All
operations involving the CACR, CAAR, and VBR are long-word operations,
whether these registers are used as the source or the destination operand.
The alternate function code registers (SFC and DFC) are 32-bit registers with
only bits 2:0 implemented that contain the address space values (FCO-FC2)
for the read or write operands of MOVES, PLOAD, PFLUSH, and PTEST in-
structions. The MOVEC instruction is used to transfer values to and from the
alternate function code registers. These are long-word transfers; the upper
29 bits are read as zeros and are ignored when written.
The remaining control registers in the supervisor programming model are
used by the memory management unit (MMU). The CPU root pointer (CRP)
and supervisor root pointer (SRP) contain pointers to the user and supervisor
address translation trees. Transfers of data to and from these 64-bit registers
are quad-word transfers. The translation control register (TC) contains control
information for the MMU. The MC68030 always uses long-word transfers to
access this 32-bit register. The transparent translation registers (TIO and TT1)
also contain 32 bits each; they identify memory areas for direct addressing
without address translation. Data transfers to and from these registers are
long-word transfers. The MMU status register (MMUSR) stores the status of
the MMU after execution of a PTEST instruction. It is a 16-bit register, and
transfers to and from the MMUSR are word transfers. Refer to SECTION 9
MEMORY MANAGEMENT UNIT
for more detail.
2.3 ORGANIZATION OF DATA IN MEMORY
Memory is organized on a byte-addressable basis where lower addresses
correspond to higher order bytes. The address, N, of a long-word data item
corresponds to the address of the most significant byte of the highest order
word. The lower order word is located at address N
+
2, leaving the least
significant byte at address N
+
3 (refer to Figure 2-1). Notice that the MC68030
MOTOROLA
MC68030 USER'S MANUAL
2-5
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