Data Bus; Data Strobe; Data Buffer Enable; Bus Cycle.termination Signals - Motorola MC68030 User Manual

7.1.4 Data Bus
The data bus signals (00-031) comprise a bidirectional, non multiplexed par-
allel bus that contains the data being transferred to or from the processor.
A read or write operation may transfer 8, 16, 24, or 32 bits of data (one, two,
three, or four bytes) in one bus cycle. During a read cycle, the data is latched
by the processor on the last falling edge of the clock for that bus cycle. For
a write cycle, all 32 bits of the data bus are driven, regardless of the port
width or operand size. The processor places the data on the data bus one-
half clock cycle after AS is asserted in a write cycle.
7.1.5 Data Strobe
The data strobe (OS) is a timing signal that applies to the data bus. For a
read cycle, the processor asserts OS to signal the external device to place
data on the bus. It is asserted at the same time as AS during a read cycle.
For a write cycle, OS signals to the external device that the data to be written
is valid on the bus. The processor asserts OS one full clock cycle after the
assertion of AS during a write cycle.
7.1.6 . Data Buffer Enable
The data buffer enable signal (DBEN) can be used to enable external data
buffers while data is present on the data bus. During a read operation, DBEN
is asserted one clock cycle after the beginning of the bus cycle and is negated
as OS is negated. In a write operation, DBEN is asserted at the time AS is
asserted and is held active for the duration of the cycle. In a synchronous
system supporting two-clock bus cycles, DBEN timing may prevent its use.
7.1.7 Bus Cycle Termination Signals
During asynchronous bus cycles, external devices assert the data transfer
and size acknowledge signals (DSACKO and/or DSACK1) as part of the bus
protocol. During a read cycle, the assertion of DSACKx signals the processor
to terminate the bus cycle and to latch the data. During a write cycle, the
assertion of DSACKx indicates that the external device has successfully stored
the data and that the cycle may terminate. These signals also indicate to the
processor the size of the port for the bus cycle just completed, as shown in
Table 7-1. Refer to 7.3.1 Asynchronous Read Cycle for timing relationships
of DSACKO and DSACK1.
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MC68030 USER'S MANUAL 7-5