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7.2.5.2.2 Address Retry (ARTRY)-Input
Following are the state meaning and timing comments for the ARTRY input signal.
State Meaning
Asserted-If the MPC750 is the address bus master, ARTRY
indicates that the MPC750 must retry the preceding address tenure
and immediately negate BR (if asserted). If the associated data
tenure has already started, the MPC750 also aborts the data tenure
immediately, even if the burst data has been received. If the MPC750
is not the address bus master, this input indicates that the MPC750
should immediately negate BR to allow an opportunity for a copy-
back operation to main memory after a snooping bus master asserts
ARTRY. Note that the subsequent address presented on the address
bus may not be the same one associated with the assertion of the
ARTRY signal.
NegatedlHigh Impedance-Indicates that the MPC750 does not
need to retry the last address tenure.
Timing Comments Assertion-May occur as early as the second cycle following the
assertion of TS, and must occur by the bus clock cycle immediately
following the assertion of AACK if an address retry is required.
Negation-Must occur two bus clock cycles after the assertion of
AACK.
7.2.6 Data Bus Arbitration Signals
Like the address bus arbitration signals, data bus arbitration signals maintain an orderly
process for determining data bus mastership. Note that there is no data bus arbitration signal
equivalent to the address bus arbitration signal BR (bus request), because, except for
address-only transactions, TS implies data bus requests. For a detailed description on how
these signals interact, see Section 8.4.1, "Data Bus Arbitration."
One special signal, DBWO, allows the MPC750 to be configured dynamically to write data
out of order with respect to read data. For detailed information about using DBWO, see
Section 8.10, "Using Data Bus Write Only."
7.2.6.1 Data Bus Grant (DBG)-Input
The data bus grant (DBG) signal is an input-only signal on the MPC750. Following are the
state meaning and timing comments for the DBG signal.
State Meaning
Asserted-Indicates that the MPC750 may, with the proper
qualification, assume mastership ofthe data bus. The MPC750
derives a qualified data bus grant when DBG is asserted and DBB,
DRTRY, and ARTRY are negated; that is, the data bus is not busy
(DBB is negated), there is no outstanding attempt to retry the current
data tenure (DRTRY is negated), and there is no outstanding attempt
to perform an ARTRY of the associated address tenure.
Negated-Indicates that the MPC750 must hold off its data tenures.
Chapter 7. Signal Descriptions
7-15
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