Timer Control Register (Tcr) - Motorola MC68HC05T16 Technical Data Manual

contains the free-running counter value that corresponds to the most recent input capture.After a
read of the input capture register MSB ($12), the counter transfer is inhibited until the LSB ($13)
is also read. This characteristic causes the time used in the input capture software routine and its
interaction with the main program to determine the minimum pulse period. A read of the input
capture register LSB ($13) does not inhibit the free-running counter transfer since they occur on
opposite edges of the internal bus clock.
5.1.4

Timer Control Register (TCR)

Address bit 7
$10 ICIE
The TCR is a read/write register containing five control bits. Four bits control interrupts associated
with each of the four flag bits found in the Timer Status register. The other bit controls which edge
is significant to the input capture edge detector. The Timer Control register and the free-running
counter are the only sections of the timer affected by reset.
Definition of each bit is as follows:
ICIE - Input Capture Interrupt Enable
1 (set) – Input Capture interrupt enabled.
0 (clear) – Input Capture interrupt disabled.
OC0IE - Output Compare Interrupt Enable
1 (set) – Output Compare 0 interrupt enabled.
0 (clear) – Output Compare 0 interrupt disabled.
OC1IE - Output Compare Interrupt Enable
1 (set) – Output Compare 1 interrupt enabled.
0 (clear) – Output Compare 1 interrupt disabled.
TOVFIE - Timer Overflow Interrupt Enable
1 (set) – Timer Overflow interrupt enabled.
0 (clear) – Timer Overflow interrupt disabled.
IEDG - Input Edge
1 (set) – TCAP is positive-going edge sensitive.
0 (clear) – TCAP is negative-going edge sensitive.
MC68HC05T16
bit 6 bit 5 bit 4
OC0IE OC1IE TOVFIE
TIMERS
bit 3 bit 2 bit 1
IEDG
State
bit 0
on reset
0000 0000
TPG
MOTOROLA
5-5
5