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7.5.2 External Boot ROM Control
The MOD input signal is used to determine the location of the boot ROM device dur-
ing hardware reset. If an external boot ROM is used instead of the internal ROM, the
CS0 output can select the external ROM coming out of reset.
If MOD is driven to a logic-low level four LOW_REFCLK clock cycles before RSTOUT
negation, and the CSEN0 bit is enabled (the default state on reset), then the internal
ROM is disabled, and CS0 is asserted for the first CPU cycle. The internal ROM is
disabled for the first CPU access only and is available for subsequent accesses. The
CS0 access uses default values of 15 wait states and a 16-bit port size.
If MOD is driven to a logic-high level four LOW_REFCLK clock cycles before
RSTOUT negation, then the internal ROM is enabled, and the CPU fetches the first
word from internal ROM.
7.5.3 Programmable Output Generation
Unused chip select outputs can be configured to provide a programmable output sig-
nal. (This functionality is not provided for the CS0 output signal. When the CSEN0 bit
is cleared, CS0 is always inactive.) To operate as a programmable output pin, the cor-
responding CSENx control bit must be cleared.
7.5.4 Bus Watchdog Operation
The EIM contains a bus watchdog timer that monitors the length of all requested
accesses from the CPU. If an access does not terminate (i.e., the bus watchdog timer
does not receive an internal TA or TEA) within 128 clocks of being initiated, the
watchdog timer expires and forces the access to be terminated by asserting a TEA
signal to the CPU. The bus watchdog timer is automatically reset to a count of zero
after the termination of each access. If an internal CPU peripheral does not terminate
its access to the CPU or if the CPU accesses an unmapped location, the bus watch-
dog times out to prevent the CPU from locking up.
7.5.5 Error Conditions
The following conditions cause TEA to be asserted to the CPU:
• An access to a disabled chip select (i.e., an access to a mapped chip-select
address space when the CSEN bit in the corresponding CS control register is
cleared).
• A write access to a write-protected chip-select address space (i.e., the WP bit in
the corresponding CS control register is set).
• A user access to a supervisor-protected chip-select address space (i.e., the SP
bit in the corresponding CS control register is set).
• Bus watchdog time out when an access does not terminate within 128 clocks of
being initiated. See 7.5.4 Bus Watchdog Operation for a description of the bus
watchdog operation.
• A user access to a supervisor-protected internal ROM or RAM (i.e., the corre-
sponding SP bit in the EIM configuration register is set), or user access to
peripheral space.
MOTOROLA
7-6
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Freescale Semiconductor, Inc.
EXTERNAL INTERFACE MODULE
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Go to: www.freescale.com
MMC2001
REFERENCE MANUAL
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