Dar, Dsisr, And Bar Operation - Motorola MPC860 PowerQUICC User Manual

Table 5-6 lists supervisor-level SPRs defined by the PowerPC architecture.
SPR Number
Decimal SPR[5Ð9] SPR[0Ð4]
18 00000 10010
19 00000 10011
22 00000 10110
26 00000 11010
27 00000 11011
272 01000 10000
273 01000 10001
274 01000 10010
275 01000 10011
284 01000 11100
285 01000 11101
287 01000 11111
1
Any read (mftb) to this address causes an implementation-dependent software emulation exception.

5.1.2.1 DAR, DSISR, and BAR Operation

The LSU updates the DAR, DSISR, and BAR when an exception is taken.
¥ When a bus error occurs, the data address register (DAR) is loaded with the effective
address. For instructions that generate multiple accesses, the effective address of the
Þrst offending tenure is loaded.
¥ The DSI status register (DSISR) notiÞes the error handler when an exception is
caused by a load or store. For a data MMU error, the data MMU loads the DSISR
with error status. For alignment exceptions, the DSISR is loaded with the instruction
information as deÞned by the PowerPC architecture.
MOTOROLA
Table 5-6. Supervisor-Level PowerPC SPRs
Name
DSISR See the Programming Environments
Manual and Section 5.1.2.1, ÒDAR,
DSISR, and BAR Operation.Ó
DAR See the Programming Environments
Manual and Section 5.1.2.1, ÒDAR,
DSISR, and BAR Operation.Ó
DEC See Section 11.8.1, ÒDecrementer
Register (DEC),Ó and in Chapter 15,
ÒClocks and Power ControlÓ
SRR0 See SRR0 settings for individual
exceptions in Chapter 7, ÒExceptions.Ó
SRR1 See SRR1 settings for individual
exceptions in Chapter 7, ÒExceptions.Ó
SPRG0 See the Programming Environments
Manual.
SPRG1
SPRG2
SPRG3
1
TBL write See Section 11.9, ÒThe PowerPC
Timebase
1
TBU write
and Power Control.Ó
PVR Section 5.1.2.3.2, ÒProcessor Version
Register.Ó
Chapter 5. PowerPC Core Register Set
Part II. PowerPC Microprocessor Module
Comments
,Ó
and Chapter 15, ÒClocks
Serialize Access
Write: Full sync
Read: Sync relative to
load/store operations
Write: Full sync
Read: Sync relative to load/
store operations
Write
Write
Write
Write
Write (as a store)
No (read-only register)
5-5