Interrupt Controller; Overview - Motorola Freescale Semiconductor M-Core MMC2001 Reference Manual

10.1 Overview

The interrupt controller module collects requests from multiple interrupt sources and
provides an interface to the M•CORE interrupt control lines.
The MMC2001 interrupt controller supports up to 32 interrupt sources (although not
all are currently defined). The processor supports two categories of interrupts: normal
and fast.
The interrupt controller performs the following functions:
• Indicates pending interrupt sources via a register
• Independently enables/disables any interrupt source
• Selects normal or fast interrupt request for any interrupt source
• Provides a mechanism for software to schedule an interrupt.
The interrupt controller consists of a set of control registers and associated logic to
perform interrupt masking and priority support.
The interrupt source register (INTSRC) is a 32-bit control register with a single inter-
rupt source associated with each bit. One or more interrupt lines are routed from
each interrupt source to the INTSRC register. This allows up to 32 distinct interrupt
sources in an implementation.
A corresponding 32-bit normal interrupt enable register (NIER) allows individual bit
masking of the INTSRC register, and a normal interrupt pending register (NIPND)
indicates pending normal interrupt requests. A logical AND is performed on the
INTSRC register and the content of the NIER register to form the content of the nor-
mal interrupt pending (NIPND) register. A logical bit-wise OR is performed on all the
NIPND register bits to form the INT signal routed to the CPU core. This core input sig-
nal is maskable by a bit in the PSR.
Two registers support fast interrupt requests. The fast interrupt enable register (FIER)
allows individual bit masking of the INTSRC register, and the fast interrupt pending
register (FIPND) indicates pending fast interrupt requests. A logical AND is performed
on the INTSRC register and the content of the FIER register to form the content of the
fast interrupt pending (FIPND) register. A logical bit-wise OR is performed on the
FIPND register bits to form the FINT signal routed to the CPU core. This core input
signal is maskable by a bit in the PSR.
These registers are readable by software. In addition, the NIER and FIER registers
are writable. Attempted writes to read-only registers are ignored. Access these regis-
ters with 32-bit loads and stores only.
MMC2001
REFERENCE MANUAL
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SECTION 10

INTERRUPT CONTROLLER

INTERRUPT CONTROLLER
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