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Chapter 1
MPC860 Overview
10
10
The MPC860 PowerPCª Quad Integrated Communications Controller (PowerQUICCª)
is a versatile one-chip integrated microprocessor and peripheral combination that can be
used in a variety of controller applications. It particularly excels in both communications
and networking systems. Unless otherwise speciÞed, the PowerQUICC unit is referred to
as the MPC860 in this manual.
The MPC860 is a PowerPC architecture-based derivative of MotorolaÕs MC68360 Quad
Integrated Communications Controller (QUICCª). The CPU on the MPC860 is a 32-bit
PowerPC implementation that incorporates memory management units (MMUs) and
instruction and data caches. The communications processor module (CPM) from the
MC68360 QUICC has been enhanced by the addition of the inter-integrated controller
2
(I
C) channel. Digital signal processing (DSP) functionality has been added to the CPM.
The memory controller has been enhanced, enabling the MPC860 to support any type of
memory, including high-performance memories and new types of DRAMs. A PCMCIA
socket controller supports up to two sockets. A real-time clock has also been integrated.
The purpose of this manual is to describe the operation of all the MPC860 functionality
with concentration on the I/O functions. Additional information can be found in PowerPC
Microprocessor Family: The Programming Environments.
1.1 Features
The following list summarizes the key MPC860 features:
¥ Embedded PowerPC core
¥ Single issue, 32-bit version of the core (compatible the PowerPC architecture
deÞnition) with 32, 32-bit general-purpose registers (GPRs)
Ñ The core performs branch prediction with conditional prefetch, without
conditional execution
Ñ 4-Kbyte data cache and 4-Kbyte instruction cache
Ñ Instruction and data caches are two-way, set-associative, physical address, least
recently used (LRU) replacement, lockable on-line granularity
Ñ MMUs with 32 entry TLB, fully associative instruction and data TLBs
MOTOROLA
Chapter 1. MPC860 Overview
1-1
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