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This section gives a short description of the M•CORE CPU features and some basic
bus interface information.
2.1 M•CORE Overview
The 32-bit M•CORE microRISC engine represents a new family of Motorola micropro-
cessor core products. The processor architecture has been designed for high-perfor-
mance and cost-sensitive embedded control applications, with particular emphasis
on reduced system power consumption. This makes the M•CORE suitable for bat-
tery-operated, portable products, as well as for highly integrated parts designed for a
high temperature environment.
Total system power consumption is dictated by various components in addition to the
processor core. In particular, memory power consumption (both on-chip and external)
is expected to dominate overall power consumption of the core-plus-memory sub-
system. With this factor in mind, the instruction set architecture (ISA) for M•CORE
makes the trade-off of absolute performance capability versus total energy consump-
tion in favor of reducing the overall energy consumption, while maintaining an accept-
ably high level of performance at a given clock frequency.
M•CORE is a streamlined execution engine that provides many of the same perfor-
mance enhancements as mainstream reduced instruction set computer (RISC)
designs. Fixed length instruction encoding and a strict load/store architecture mini-
mize control complexity and overhead. The goal of minimizing the overhead of mem-
ory system energy consumption is achieved by adopting a (relatively) short 16-bit
instruction encoding. This choice significantly lowers the memory bandwidth needed
to sustain a high rate of instruction execution.
Code density statistics for a number of applications show relative code density com-
petitive in comparison to complex instruction set computer (CISC) designs, and
implementation statistics show a large reduction in complexity and overhead relative
to a CISC approach.
In addition to substantial cost and performance benefits, M•CORE also offers advan-
tages in power consumption and power management. M•CORE minimizes power dis-
sipation by using a fully static design, dynamic power management, and low-voltage
operation. The M•CORE automatically powers-down internal functional blocks that
are not needed on a clock-by-clock basis. Power conservation modes are also pro-
vided for absolute power conservation on a coarser granularity.
MMC2001
REFERENCE MANUAL
All manuals and user guides at all-guides.com
Freescale Semiconductor, Inc.
SECTION 2
INTEGER CPU
INTEGER CPU
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
2-1
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