Floating-Point Status And Control Register (Fpscr) - Motorola MPC533 Reference Manual

User Instruction Set Architecture (UISA) Register Set
supports the double-precision, floating-point format. Every instruction that interprets the
contents of an FPR as a floating-point value does so using the double-precision
floating-point format. Therefore, all floating-point numbers are stored in double-precision
format.
All floating-point arithmetic instructions operate on data located in FPRs and, with the
exception of the compare instructions (which update the CR), place the result into an FPR.
Information about the status of floating-point operations is placed into the floating-point
status and control register (FPSCR) and in some cases, after the completion of the
operation's writeback stage, into the CR. For information on how the CR is affected by
floating-point operations, see Section 3.7.4, "Condition Register (CR)."
MSB
0
Reset
3.7.3

Floating-Point Status and Control Register (FPSCR)

The FPSCR controls the handling of floating-point exceptions and records status resulting
from the floating-point operations. FPSCR[0:23] are status bits. FPSCR[24:31] are control
bits.
FPSCR[0:12] and FPSCR[21:23] are floating-point exception condition bits. These bits are
sticky, except for the floating-point enabled exception summary (FEX) and floating-point
invalid operation exception summary (VX). Once set, sticky bits remain set until they are
cleared by an mcrfs, mtfsfi, mtfsf, or mtfsb0 instruction.
Table 3-4 summarizes which bits in the FPSCR are sticky status bits, which are normal
status bits, and which are control bits.
3-14
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Figure 3-5. Floating-Point Registers (FPRs)
Table 3-4. FPSCR Bit Categories
Bits
[0], [3:12], [21:23] Status, sticky
[1:2], [13:20] Status, not sticky
[24:31] Control
MPC533 Reference Manual
FPR0
FPR1
. . .
. . .
FPR31
Unchanged
Type
LSB
63
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