Simulation; Functional Description; Ports And Attributes; Implementation - Xilinx Virtex-6 FPGA User Manual

Simulation

Functional Description

For simulating a design with GTH transceivers, SecureIP libraries must be compiled using
the COMPXLIB tool. For more details on SecureIP, COMPXLIB, and setting up the
simulation environment, refer to UG626, Synthesis and Simulation Design Guide.

Ports and Attributes

There are no simulation-only ports.
The GTHE1_QUAD primitive has attributes intended only for simulation.
simulation-only attributes of the GTHE1_QUAD primitive. The names of these attributes
start with SIM_.
.
Table 1-6: Simulation Attributes
Attribute
SIM_GTHRESET_SPEEDUP
SIM_VERSION

Implementation

Functional Description
This section provides the information needed to map Virtex-6 FPGA GTH transceivers
instantiated in a design to device resources, including:
•
•
•
It is a common practice to define the location of the GTH Quad early in the design process
to ensure correct usage of clock resources and to facilitate signal integrity analysis during
board design. The implementation flow facilitates this practice through the use of location
constraints in the UCF.
While this section describes how to instantiate GTH clocking components, the details of
the different GTH transceiver clocking options are discussed in
Distribution and Selection, page
The position of the GTH Quad is specified by an XY coordinate system that describes the
column number and its relative position within that column. In the Virtex-6 HXT device,
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010
Type
Integer This attribute shortens the number of DCLK cycles required to finish the
GTHRESET sequence during simulation (deassertion of GTHRESET to
the assertion of GTHINITDONE).
0: The GTHRESET sequence is simulated with its original duration
(standard initialization is approximately 360 μs for a 50
1: The GTHRESET cycle time is shortened (fast initialization is
approximately 50 μs for a 50
Real This attribute selects the simulation version to match different steppings
of silicon. The default for this attribute is 1.0.
The location of the GTH transceiver on the available device and package
combinations.
The pad numbers of external signals associated with each GTH transceiver.
How the GTH Quad and clocking resources instantiated in a design are mapped to
available locations with a user constraints file (UCF).
www.xilinx.com
Description
MHz DCLK).
45.
Simulation
Table 1-6 lists the
MHz DCLK).
Reference Clock
31