Simulation; Functional Description - Xilinx Virtex-6 FPGA User Manual

X-Ref Target - Figure 1-4
3.

Simulation

Functional Description

Simulations using GTX transceivers have specific prerequisites that the simulation
environment and the test bench must fulfill.
The Synthesis and Simulation Design Guide explains how to set up the simulation
environment for supported simulators depending on the used Hardware Description
Language (HDL). This design guide can be downloaded from the Xilinx website.
The prerequisites for simulating a design with GTX transceivers are:
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www.BDTIC.com/XILINX
Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
/FPGA Features & Design/IO Interfaces
See Figure 1-4.
Figure 1-4: Virtex-6 FPGA GTX Transceiver Wizard
Double-click V6 GTX Wizard to launch the Wizard.
Simulator with support for SecureIP models, which are encrypted versions of the
Verilog HDL used for implementation of the modeled block.
SecureIP is a new IP encryption methodology. To support SecureIP models, a Verilog
LRM - IEEE Std 1364-2005 encryption compliant simulator is required.
Mixed-language simulator for VHDL simulation.
www.xilinx.com
Simulation
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