After Changing The Reference Clock To Rx Pll; After Assertion/Deassertion Of Rxpowerdown; Rx Rate Change With Rx Elastic Buffer Enabled; Rx Rate Change With Rx Elastic Buffer Bypassed - Xilinx Virtex-6 FPGA User Manual

If the reference clock(s) or GTX transceiver(s) are powered up after configuration,
GTXRXRESET must be asserted to allow the RX PLL(s) to lock.

After Changing the Reference Clock to RX PLL

Whenever the reference clock input to GTX RX PLL is changed, the RX PLL must be reset
afterwards to ensure that it locks to the new frequency. The GTXRXRESET port must be
used for this purpose. Refer to

After Assertion/Deassertion of RXPOWERDOWN

After deassertion of the RXPOWERDOWN signal, GTXRXRESET must be asserted.

RX Rate Change with RX Elastic Buffer Enabled

After the completion of a rate change initiated via the RXRATE[1:0] port, the RX PCS must
be reset using RXRESET. To automatically reset the RX elastic buffer after a rate change,
RX_EN_RATE_RESET_BUF must be set to TRUE.

RX Rate Change with RX Elastic Buffer Bypassed

After the completion of a rate change initiated via the RXRATE[1:0] port, the RX PCS must
be reset using RXRESET. Phase alignment must be performed again. RXRATEDONE or
PHYSTATUS can be used to detect the completion of the rate change (see
Output Control, page
alignment procedure.

RX Parallel Clock Source Reset

The clocks driving RXUSRCLK and RXUSRCLK2 must be stable for correct operation.
These clocks are often driven from an MMCM in the FPGA to meet phase and frequency
requirements. If the MMCM loses lock and begins producing incorrect output, RXRESET
must be used to hold the RX PCS in reset until the clock source is locked again.
If the RX buffer is bypassed and phase alignment is in use, phase alignment must be
performed again after the clock source relocks.
See

After Remote Power-Up

If the remote source of incoming data is powered up after the GTX transceiver that is
receiving its data is operating, the RX CDR must be reset to ensure a clean lock to the
incoming data. When the guidelines in
electrical idle reset situation is automatically managed.

Electrical Idle Reset

When the differential voltage of the RX input to a GTX transceiver drops to OOB or
electrical idle levels, the RX CDR can be pulled out of lock by the apparent sudden change
in frequency. When the guidelines in
electrical idle reset situation is automatically managed.
www.BDTIC.com/XILINX
Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
207). See
RX Buffer Bypass, page 231
www.xilinx.com
Reference Clock Selection, page 102
RX Buffer Bypass, page 231
for details on the phase alignment procedure.
Link Idle Reset Support, page 264
Link Idle Reset Support, page 264
RX Initialization
for more details.
RX Fabric Clock
for details on the phase
are followed, the
are followed, the
267