Evm Assembly Drawings And Layout; Tps40193Evm-001 Gain And Phase Vs Frequency - Texas Instruments TPS40193EVM-001 User Manual

EVM Assembly Drawings and Layout

6.5 Control Loop Bode Plot
6.5.1 Low Line (V = 8V)
IN
Figure 10. TPS40193EVM-001 Gain and Phase vs Frequency
6.5.2 High Line (V = 14V)
IN
Figure 11. TPS40193EVM-001 Gain and Phase vs Frequency
7 EVM Assembly Drawings and Layout
Figure 12 through
EVM has been designed using a 4-layer, 2oz., copper-clad PCB (2.5in x 2.5in), with all components in a
1.54in x 0.76in active area on the top side and all active traces to the top and bottom layers of the board.
This configuration allows the user to easily view, probe and evaluate the TPS40193 control IC in a
practical, double-sided application. Moving components to both sides of the PCB or using additional
internal layers can offer additional size reduction for space-constrained systems.
Unless otherwise specified, these figures illustrate the view from the top side of the PCB.
Note: Board layouts are not to scale. These figures are intended to show how the board is laid
out; they are not intended to be used for manufacturing TPS40193EVM-001 PCBs.
14 Using the TPS40193EVM-001
60
Gain
40
20
0
20
-
V = 8V
IN
40
-
V = 1.8V
OUT Bandwidth: 46kHz
I = 10A
Phase Margin:
OUT
60
-
100 1k
60
Gain
40
20
0
20
-
V = 14V
IN
40
-
V = 1.8V
Bandwidth: 68kHz
OUT
I = 10A
Phase Margin: Frequency (Hz)
OUT
60
-
100 1k
Figure 17 show the design of the TPS40193EVM-001 printed circuit board (PCB). The
Phase
Margin
53°
10k 100k 1M
Frequency (Hz)
Phase
Margin
45°
10k 100k 1M
www.ti.com
180
150
120
90
60
30
0
30
-
60
-
90
-
120
-
150
-
180
-
180
150
120
90
60
30
0
30
-
60
-
90
-
120
-
150
-
180
-
SLUU274 – May 2007
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