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The
pin of the processor connects to a 24.576 MHz oscillator. The
CLKIN
core frequency of the processor is derived by multiplying the frequency at
the
pin by a value determined by the state of the processor pins,
CLKIN
and
CLKCFG1
CLKCFG0
the
switch (see
SW10
on page
2-11). By default, the EZ-KIT Lite gives a core frequency of
147.456 MHz. It is possible to increase the speed of the processor by
changing the value of the
The
switch also configures the boot mode of the processor. The
SW10
EZ-KIT Lite is capable of Parallel Port boot and SPI Master Boot. By
default, the EZ-KIT Lite boots from the parallel port. For information
about configuring the boot modes, see
Select Switch (SW10)" on page
Parallel Port
The parallel port (PP) of the ADSP-21364 processor consists of a 16-bit
multiplex address/data memory bus (
pin (
). The interface does not have any memory select pins; these sig-
ALE
nals must be generated by decoding the address.
The PP connections to the EZ-KIT Lite are shown in
is connected to an 8-bit parallel flash memory, an 8-bit SRAM memory,
and eight general-purpose LEDs. The upper three address bits are con-
nected to a 3-to-8 decoder, providing eight memory select pins. See
"External Memory" on page 1-6
flash and SDRAM memories.
Because the PP is a multiplexed address/data memory bus, two 8-bit
latches are used to latch the upper address bits. Additional latch is used to
drive the LEDs. The latter allows the LED values to be written to as if
they were at a memory location. For more information about using the
LEDs, refer to the
ADSP-21364 EZ-KIT Lite Evaluation System Manual
EZ-KIT Lite Hardware Reference
. The value at these pins is determined by the state of
"Boot Mode and Clock Ratio Select Switch (SW10)"
register.
PMCTL
2-11.
for more information about accessing the
"LEDs and Push Buttons" on page
"Boot Mode and Clock Ratio
) and an address latch-enable
AD15–0
Figure
1-9.
2-2. The PP
2-3
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