Csr Memory Map; Table 151. Core Global Control And Status Registers (Csrs); Figure 358. Csr Memory Map - ST STM32F205 series Reference Manual

USB on-the-go full-speed (OTG_FS)
29.16.1

CSR memory map

The host and device mode registers occupy different addresses. All registers are
implemented in the AHB clock domain.
1. x = 3 in device mode and x = 7 in host mode.
Global CSR map
These registers are available in both host and device modes.

Table 151. Core global control and status registers (CSRs)

Acronym
OTG_FS_GOTGCTL
OTG_FS_GOTGINT
OTG_FS_GAHBCFG
OTG_FS_GUSBCFG
OTG_FS_GRSTCTL
984/1378

Figure 358. CSR memory map

0000h
0400h
0800h
Device mode CSRs (1.5 Kbyte)
0E00h
Power and clock gating CSRs (0.5 Kbyte)
1000h
Device EP 0/Host channel 0 FIFO (4 Kbyte)
2000h
Device EP1/Host channel 1 FIFO (4 Kbyte)
3000h
Device EP (x – 1)
Device EP x
2 0000h
Direct access to data FIFO RAM
for debugging (128 Kbyte)
3 FFFFh
Address
offset
0x000 OTG_FS control and status register (OTG_FS_GOTGCTL) on page 989
0x004 OTG_FS interrupt register (OTG_FS_GOTGINT) on page 990
0x008 OTG_FS AHB configuration register (OTG_FS_GAHBCFG) on page 992
0x00C OTG_FS USB configuration register (OTG_FS_GUSBCFG) on page 993
0x010 OTG_FS reset register (OTG_FS_GRSTCTL) on page 995
Core global CSRs (1 Kbyte)
Host mode CSRs (1 Kbyte)
(1) (1)
/Host channel (x – 1)
(1) (1)
/Host channel x FIFO (4 Kbyte)
Reserved
Register name
RM0033 Rev 8
DFIFO
push/pop
to this region
FIFO (4 Kbyte)
DFIFO
debug read/
write to this
region
RM0033
ai15615b