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21.4 Automatic Algorithm of Flash Memory
Commands for activating the automatic algorithms of the flash memory can be divided
into four types: Read/Reset, Write, Chip Erase, and Sector Erase. The Sector Erase
command is further divided into a Sector Erase Temporary Stop command and a
Sector Erase Restart command.
I Command sequence
To activate the automatic algorithm, write half word data (16 bits) to the flash memory
continuously one to six times. This is called a command.
If incorrect addresses and data are written or if addresses and data are written in incorrect
order, the flash memory is reset to read mode.
Table 21.4-1 "Command sequence" lists the commands used when data is written to, or erased
from the flash memory. (The item "Address" in this table means a CPU address.)
Table 21.4-1 Command sequence
1st bus write
Bus
Command
write
sequence
cycle
dress
Read/Reset
1
XXXXX
Read/Reset
4
D5555
Write
4
D5555
Chip Erase
6
D5555
Sector Erase
6
D5555
Sector Erase Temporary
Entering address XXXXX
Stop
Sector Erase Restart
Entering address XXXXX
Auto Select
3
D5555
Continuation
3
D5555
Mode
Continuous
2
XXXXX
Write
Continuous
2
XXXXX
Mode Reset
The commands used in word mode are the same as those in byte mode. Bits not listed in this table can have any value.
All addresses and data are represented in hexadecimal numbers.
(RA): Read address
(PA): Write address
(SA): Sector address (specification of any address in the sector)
(RD): Read data
(PD): Write data
The Sector Erase Temporary Stop command (B0H) and Sector Erase Restart command (30H) are valid only when a sector is being erased.
Both Reset commands can reset the flash memory to read mode.
2nd bus write
cycle
cycle
Ad-
Ad-
Data
Data
dress
F0
-
-
H
H
AA
CAAAB
55
H
H
H
H
AA
CAAAB
55
H
H
H
H
AA
CAAAB
55
H
H
H
H
AA
CAAAB
55
H
H
H
H
, data (B0) temporarily stops sector erase processing.
H
, data (30) temporarily stops sector erase processing and then restarts it.
H
AA
CAAAB
55
H
H
H
H
AA
CAAAB
55
H
H
H
H
A0
(PA)
(PD)
H
H
F0
H
90
XXXXX
H
H
H
00
H
3rd bus write
4th bus read/
cycle
write cycle
Ad-
Ad-
Data
dress
dress
-
-
-
D5555
F0
(RA)
H
H
D5555
A0
(PA)
H
H
D5555
80
D5555
H
H
H
D5555
80
D5555
H
H
H
D5555
90
-
H
H
D5555
20
-
H
H
-
-
-
or
-
-
-
CHAPTER 21 FLASH MEMORY
5th bus write
6th bus write
cycle
Ad-
Ad-
Data
Data
dress
dress
-
-
-
(RD)
-
-
(PD)
-
-
AA
CAAAB
55
D5555
H
H
H
AA
CAAAB
55
(SA)
H
H
H
-
-
-
-
-
-
-
-
-
-
-
-
cycle
Data
-
-
-
-
-
-
10
H
H
30
H
-
-
-
-
-
-
-
-
423
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