CHAPTER 16 DMA CONTROLLER (DMAC)
DMAC ch0 to ch4 Control/Status Registers A
The DMACA0 to 4 registers control the operation of the DMAC channels. A separate
register is provided for each channel.
■ Functions of the DMACA0 to 4 Bits
The functions of the DMACA0 to 4 bits are shown below.
[Bit 31] DENB (Dma ENaBle): DMA operation enable bit
This bit, which corresponds to a transfer channel, is used to enable and disable DMA transfer.
The activated channel starts DMA transfer when a transfer request is generated and accepted.
All transfer requests that are generated for a deactivated channel are disabled.
When the transfer on an activated channel reaches the specified count, this bit is set to "0" and transfer
The transfer can be forced to stop by writing "0" to this bit. Be sure to stop a transfer forcibly ("0"
write) only after temporarily stopping DMA using the PUAS bit [Bit30 of DMACA]. If the transfer is
forced to stop without first temporarily stopping DMA, DMA stops but the transferred data cannot be
guaranteed. Check whether DMA is stopped using the DSS[2:0] bits [Bit18 to 16 of DMACB].
If a stop request is accepted during reset: Initialized to "0".
This bit is readable and writable.
If the operation of all channels is disabled by Bit15 (DMAE bit) of the DMAC all-channel control register
(DMACR), writing "1" to this bit is disabled and the stopped state is maintained. If the operation is disabled
by the above bit while it is enabled by this bit, "0" is written to this bit and the transfer is stopped (forced
DENB PAUS STRG
Disables operation of DMA on the corresponding channel (initial value).
Enables operation of DMA on the corresponding channel.
IS [4 : 0]
DTC [15 : 0]
(Initial value: 00000000_0000XXXX_XXXXXXXX_XXXXXXXX
DDN [3 : 0]
BLK [3 : 0]