Control Status Registers (Adcs1 And Adcs2); Figure 16.3.1A Control Status Registers - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

16.3 Registers and Register Details

16.3.1 Control status registers (ADCS1 and ADCS2)

These registers are used to control the A/D converter and display the status.
Control Status Registers (Upper Byte)
Address : 000037
Read/write
Initial value
Control Status Registers (Lower Byte)
Address : 000036
Read/write
Initial value
Note: Do not update ADCS1 during A/D conversion.
[bit 15] BUSY (busy flag and stop):
Read: This bit indicates the A/D converter operation. This bit is set when the A/D conversion is
activated, and cleared when the conversion ends.
Write: Writing '0' to this bit during A/D conversion forces the conversion to terminate. This features is
used for forced stop in continuous or stop mode.
'1' cannot be written to the operation display bit. With a read-modify-write instruction.
'1' is read from this bit. In single mode, this bit is cleared at the end of A/D conversion.
In continuous or stop mode, this bit is not cleared until conversion is stopped by writing '0.'
This bit is initialized to '0' upon a reset.
Do not perform forced termination and activation by software simultaneously. (BUSY=0, STRT=1)
[bit 14] INT (Interrupt): A data display bit
This bit is set when conversion data is written to ADCR.
An interrupt request is issued if this bit is set while bit 5 (INTE) is '1.' In addition, I2OS is activated if it is
enabled. Writing '1' has no effect.
This bit is cleared by writing '0' or by an I2OS interrupt clear signal.
Note: To clear this bit by writing '0,' ensure that A/D conversion is not in progress.
This bit initialized to '0' upon a reset.
[bit 13] INTE (Interrupt enable): This bit is used to enable or disable interrupts at the end of conversion..
0 Interrupts are disabled.
1 Interrupts are enabled.
Set this bit when using I2OS. I2OS is activated when an interrupt request is issued.
Upon a reset, this bit is initialized to '0.'
222 Chapter 16: A/D Converter
15 14 13
BUSY INT INTE
H
(R/W) (R/W) (R/W)
(0) (0) (0)
7 6 5
MD1 MD0 ANS2
H
(R/W) (R/W) (R/W)
(0) (0) (0)

Figure 16.3.1a Control Status Registers

12 11 10
PAUS STS1 STS0
(R/W) (R/W) (R/W)
(0) (0) (0)
4 3 2
ANS1 ANS0 ANE2
(R/W) (R/W) (R/W)
(0) (0) (0)
9 8
Bit number
STRT DA
ADCS2
(W) (R/W)
(0) (0)
1 0
Bit number
ANE1 ANE0
ADCS1
(R/W) (R/W)
(0) (0)
[initial value]
MB90580 Series