Serial Input Data Register 0, 1 (Sidr0, Sidr1) And Serial Output Data Register 0, 1 (Sodr0, Sodr1) - Fujitsu MB90335 Series Hardware Manual

CHAPTER 18 UART
18.4 Register of UART
18.4.4 Serial Input Data Register 0, 1 (SIDR0, SIDR1) and Serial
Output Data Register 0, 1 (SODR0, SODR1)
Serial input data and serial output data registers are located in the same address. They
function as a serial input data register in reading, while in writing as a serial output data
register.
■ Serial Input Data Register 0, 1 (SIDR0, SIDR1)
Figure 18.4-5 shows the bit configuration of the serial input data register.
Address
ch.0 : 000022
ch.1 : 000028
R : Read only
X : Undefined value
Serial input data register 0, 1 (SIDR0, SIDR1) is a data buffer register for receiving serial data.
• The serial data signals sent to the serial input pins (SIN0, SIN1) are converted in the shift register, and
stored in the serial input data registers 0, 1 (SIDR0, SIDR1).
• When the data length is 7 bits, the upper one bit (SIDR0, SIDR1:D7) becomes invalid.
• When the receiving data is stored in the serial input data registers 0, 1 (SIDR0, SIDR1), the receiving
data full flag bit (SSR0, SSR1: RDRF) is set to "1". When receiving interrupts are enabled (SSR0,
SSR1: RIE=1), receiving interrupt requests are generated.
• Read the serial input data registers 0, 1 (SIDR0, SIDR1) in the state that the receiving data full flag bit
(SSR0, SSR1: RDRF) is set to "1". When the receiving data full flag bit (SSR0, SSR1: RDRF) reads the
serial input data registers 0, 1 (SIDR0, SIDR1), it is automatically cleared to "0".
• If any receiving error occurs (SSR0, SSR1: PE, ORE, or FRE is "1"), the data of the serial input data
registers 0, 1 (SIDR0, SIDR1) is invalid.
400
Figure 18.4-5 Serial Input Data Register 0, 1 (SIDR0, SIDR1)
bit7 bit6
H
D7
D6
H
R R
FUJITSU MICROELECTRONICS LIMITED
bit5
bit4 bit3 bit2
D3 D2
D5 D4
R
R R R
MB90335 Series
bit1 bit0
Initial value
XXXXXXXX
D1 D0
R R
CM44-10137-6E
B