Registers Of Input Capture - Fujitsu MB91150 Series Hardware Manual

9.3.3

Registers of Input Capture

The input capture has the following two data registers:
• Input capture data register (IPCP0 to 3)
• Input capture control register (IPCP)
I Input capture data register (IPCP0 to 3)
The register configuration of the input capture data registers (IPCP0 to 3) is as follows:
Upper 8 bits of input
capture data register
Lower 8 bits of input
capture data register
The input capture data registers (IPCP0 to 3) are used to store the value of the 16-bit free-run
timer when a significant edge of the corresponding external pin input waveform is detected.
(Access this register in word units. The user cannot write any value to this register.)
I Input capture control register (ICS01, ICS23)
The register configuration of the input capture control register (ICS01, ICS23) is as follows:
Upper 8 bits of capture
control register (ICS23)
Upper 8 bits of capture
control register (ICS01)
[Bits 15, 14, 7 and 6]: ICP3, ICP2, ICP1, and ICP0
These bits are used as input-capture interrupt flags. When a significant edge of an external
input pin is detected, these bits are set to 1. When the interrupt permission bits (ICE3, ICE2,
ICE1, and ICE0) are also set, an interrupt is generated as soon as the significant edge is
detected. To clear these bits, set them to 0. Setting these bits to 12 has no effect. Read
operations with read modify write instructions always return 1 for these bits.
0
1
ICPn: n corresponds to the channel number of the input capture.
Bit15 Bit14
CP15 CP14 CP13
R R R
(X) (X) (X)
Bit7 Bit6
CP07 CP06 CP05
R R R
(X) (X) (X)
Bit7 Bit6 Bit5
ICP3 ICP2 ICE3
R/W R/W R/W
(0) (0) (0)
Bit7 Bit6 Bit5
ICP1 ICP0 ICE1
R/W R/W R/W
(0) (0) (0)
No significant edge is detected. (initial value)
A significant edge is detected.
CHAPTER 9 MULTIFUNCTIONAL TIMER
Bit13 Bit12 Bit11 Bit10
CP12 CP11 CP10
R R R
(X) (X) (X)
Bit5 Bit4 Bit3
CP04 CP03 CP02
R R R
(X) (X) (X)
Bit4 Bit3 Bit2
ICE2 EG31 EG30
R/W R/W R/W
(0) (0) (0)
Bit4 Bit3 Bit2
ICE0 EG11 EG10
R/W R/W R/W
(0) (0) (0)
Bit9 Bit8
CP09 CP08
R R
(X) (X)
Bit2 Bit1 Bit0
CP01 CP00
R R
(X) (X)
Bit1 Bit0
EG21 EG20
R/W R/W
(0) (0)
Bit1 Bit0
EG01 EG00
R/W R/W
(0) (0)
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