Block Diagram Of Low-Power Consumption Controller; Fig. 5.2 Block Diagram Of Low-Power Consumption Controller - Fujitsu MB90420/5 (A) Series Hardware Manual

5.2 Block Diagram of Low-power Consumption Controller

The low-power consumption controller consists of the following seven blocks.
• CPU Intermittent operation selector
• Standby controller
• CPU Clock controller
• Resource clock controller
• Pin high-impedance controller
• Internal reset generator
• Low-power consumption mode control register (LPMCR)
n Block diagram of low-power consumption controller
Figure 5.2 shows block diagram of low-power consumption controller.
Low-power consumption mode control register (LPMCR)
STP
RSTX
pin
Cancellation of
interrupt
Clock generation section
X0 pin
X1 pin
X0A
pin
X1A
pin

Fig. 5.2 Block Diagram of Low-power Consumption Controller

LOW-POWER CONSUMPTION MODE
SLP SPL R S T T M D
CPU Intermittent
operation selector
2
Standby
/
controller
Clock selector
SCM
PLL clock
multiplying circuit
2-divided
clock
Main clock
System
clock
generator
4-divided
clock
Sub-clock
Sub-clock
generator
C G 1 C G 0 S S R
Pin high impedance
controller
Internal reset generator
CPU Clock controller
Resource clock
Machine clock controller
Cancellation of oscillation stabilization wait
/ 2
2
/
M C M W S 1 W S 0 S C S
Clock select register (CKSCR)
2048-
4-divided
divided
clock
clock
5-5
Pin Hi- control
Z
Internal reset
Selection of intermittent cycle
CPU Clock
Stop/sleep signal
Stop signal
Resource clock
Oscillation stabilization
wait time selector
MCS CS1 CS0
4-divided
8-divided
clock
clock
Time-base timer