Table 2-2 Operating Mode Of Low-Power Consumption Modes - Fujitsu F2MC-8L Family series Hardware Manual

CPU
HARDWARE CONFIGURATION
(4) Description of operation
(a) Low-power consumption mode
This chip has three operation modes shown in the table below. The sleep
mode and stop mode reduce the power consumption. The system clock
can be selected out of three according to the system condition to minimize
power consumption.
Table 2–2 Operating Mode of Low-power Consumption Modes
Oscillation Clock
mode pulse
RUN
Oscillates
SLEEP
STOP Stop
• The SLEEP mode stops only the operating clock pulse of the CPU; other
operations are continued.
• The STOP mode stops the oscillation. Data can be held with the lowest
power consumption in this mode.
a. SLEEP mode
• Switching to Sleep mode
- Writing 1 at the SLP (bit 6) of the STBC register switches the mode to
SLEEP mode.
- The SLEEP mode is the mode to stop clock pulse operating the CPU;
only the CPU stops and the peripherals continue to operate.
- If an interrupt is requested when 1 is written at the SLP (bit 6),
instruction execution continues without switching to the SLEEP mode.
- In the SLEEP mode, the contents of registers and RAM immediately
before entering the SLEEP mode are held.
• Canceling SLEEP mode
- The SLEEP mode is canceled by inputting the reset signal or
requesting an interrupt.
- When the reset signal is input during the SLEEP mode, the CPU is
switched to the reset state and the SLEEP mode is canceled.
- When an interrupt level higher than 11 is requested from a peripheral
during the SLEEP mode, the SLEEP mode is canceled.
- When the I flag and IL bit are enable after canceling, the CPU executes
the interrupt processing like an ordinary interrupt. When they are
disabled, the CPU starts processing the next instruction given before
entering the SLEEP mode.
2– 11
Each operating clock pulse
(5 MHz clock)
Time-base
CPU
timer peripheral
2.5 MHz
2.5 MHz 2.5 MHz
Stops
Stops
Wake-up source
in each mode
Each
Various interrupt
requests
Stops External interrupt