Serial Control Register (Scr0/Scr1) - Fujitsu MB90460 Series Hardware Manual

CHAPTER 17 UART
17.4.1

Serial Control Register (SCR0/SCR1)

This register specifies parity bits, selects the stop bit and data lengths, selects a frame
data format in mode 1, clears the reception error flag, and specifies whether to enable
transmission and reception.
■ Serial Control Register (SCR0/SCR1)
bit
Address
c h . 0 : 0 0 0 0 2 1
H
c h . 1 : 0 0 0 0 2 5
H
R/W : Read/Write
: Initial value
476
Figure 17.4-2 Serial Control Register (SCR0/SCR1)
15 14 13 12 11
PEN P SBL CL A/D
R/W R/W R/W R/W R/W R/W R/W R/W
10 9 8 7
(SMR)
REC RXE TXE
TXE Transmission enable bit
0 Disables transmission
1 Enables transmission
RXE
Reception enable bit
0 Disables reception
Enables reception
1
REC
Reception error flag clear bit
0
Clears the FRE, ORE, and PE flags
1
Has no effect on the others
A/D
Address/data selection bit
0 Data frame
1 Address frame
CL
Data length selection bit
0
7 bits
1
8 bits
SBL
Stop bit length selection bit
0 1-bit length
2-bit length
1
Parity selection bit
P
Enabled only when parity is provided (PEN=1)
0 Even parity
1 Odd parity
PEN
Parity enable bit
0
Provides no parity bit
1 Provides a parity bit
0
Initial value
0 0 0 0 0 1 0 0
B