Serial Control Register (Scr) - Fujitsu F2MC-16LX Hardware Manual

17.3.2 Serial Control Register (SCR)

The serial control register (SCR) controls a transfer protocol for serial communication.
■ Serial Control Register (SCR)
Figure 17.3-3 Configuration of Serial Control Register (SCR)
Serial control register
Address:000021
Read/write
Initial value
[bit15] PEN (Parity enable)
The PEN bit specifies whether to add a parity bit when establishing serial data communication.
Table 17.3-5 Function of PEN (Parity Enable) Bit
PEN
0
1
Note:
A parity bit can be added only in the normal mode (mode 0) of asynchronous (start-stop
synchronous) communication modes, not in multiprocessor mode (mode 1) and CLK-
synchronous communication mode (mode 2).
[bit14] P (Parity)
The P bit specifies even or odd parity when adding a parity bit for data communication.
Table 17.3-6 P (Event/Odd Parity Specification Bit)
P
0
1
[bit13] SBL (Stop bit length)
The SBL bit specifies the length of a stop bit, which is a frame end mark used in
asynchronous (start-stop synchronous) communication.
15 14 13
bit
PEN P SBL
H
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0) (0) (0)
No parity [Initial value]
Parity
Even parity [Initial value]
Odd parity
12 11 10 9
CL A/D REC RXE
(0) (0) (1) (0)
Function
Function
17.3 UART Registers
8
TXE SCR
(R/W)
(0)
263