Serial Control Register (Scr) - Fujitsu F2MC-16LX Hardware Manual

21.2.2 Serial Control Register (SCR)

This section describes the configuration and functions of the serial control register
(SCR).
I Serial control register (SCR)
The bit configuration of the Serial Control Register (SCR) is illustrated below.
000021
H
The functions of the bits of the serial control register (SCR) are as follows:
[Bit 15] PEN: Parity ENable
This bit specifies whether to add a parity bit during transmission and to detect it during
receiving when processing serial data.
0
1
Note:
Parity can be added only in normal mode (Mode 0) in asynchronous (start-stop)
communication mode. Parity cannot be added in multiprocessor mode (Mode 1) or in CLK
synchronous communication (Mode 2).
[Bit 14] P: Parity
This bit specifies whether to use even or odd parity in data communications with parity.
0
1
[Bit 13] SBL: Stop Bit Length
This bit specifies the bit length of the stop bit, which is a frame end mark in asynchronous
(start-stop) communication.
0
1
15 14 13 12
PEN P SBL CL
(R/W) (R/W) (R/W) (R/W) (R/W) (W) (R/W) (R/W) Reading/writing
(0) (0) (0) (0)
No parity
Parity provided
Even parity
Odd parity
1 stop bit
2 stop bits
11 10 9 8
A/D REC RXE TXE
(0) (1) (0) (0)
CHAPTER 21 UART
Serial control (SCR)
Initial value
399