Serial Control Register (Scr0/1/2/3/4) - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

12.3 Register and Register Details

12.3.2 Serial Control Register (SCR0/1/2/3/4)

Serial control register
Address : 000021
000025
000029
000083
000089
Read/write
Initial value
The SCR register controls the transfer protocol for serial communications.
[bit 15] PEN (Parity enable):
This bit is used to specify whether to perform serial data communication using a parity bit.
0 With parity
1 Without parity
Note: A parity bit can be added only in normal asynchronous communication mode (mode 0).
No parity bit can be added in multi-processor mode (mode 1) or CLK synchronous
communication mode (mode 2).
[bit 14] P (Parity):
This bit is used to specify an even- or odd-numbered parity for data communications with parity.
0 Even-numbered parity
1 Odd-numbered parity
[bit 13] SBL (Stop bit length)
This bit is used to specify the length of the stop bit, which is used as a frame end mark in asynchronous
communications.
0 1 stop bit
1 2 stop bits
[bit 12] CL (Character length):
This bit is used to specify the data length of each frame to be sent or received.
0 7-bit data
1 8-bit data
Note: 7-bit data can be handled only in normal synchronous communication mode (mode 0).
Specify 8-bit data in multi-processor mode (mode 1) or CLK synchronous communica-
tion mode (mode 2).
128 Chapter 12: UART
H
15 14
H
H
PEN P
H
H
(R/W) (R/W)
(0) (0)
13 12 11
SBL CL A/D
(R/W) (R/W) (R/W)
(0) (0) (0)
10 9 8
REC RXE TXE
(R/W) (R/W) (R/W)
(1) (0) (0)
[initial value]
[initial value]
[initial value]
[initial value]
Bit number
SCR0
SCR1
SCR2
SCR3
SCR4
MB90580 Series