Serial Control Register 0 To 3 (Scr0 To Scr3) - Fujitsu F2MC-16LX Hardware Manual

21.4.1

Serial Control Register 0 to 3 (SCR0 to SCR3)

Serial control registers 0 to 3 (SCR0 to SCR3) are responsible for setting parity,
selecting the stop bit length and data length, selecting the frame data format in mode 1,
clearing receiving error flags, and enabling/disabling send and receive operations.
Serial Control Register 0 to 3 (SCR0 to SCR3)
Address
ch0 : 000021
ch1 : 000027
ch2 : 00002D
ch3 : 000033
R/W : Readable/Writable
W: Write only
Figure 21.4-2 Serial Control Register 0 to 3 (SCR0 to SCR3)
bit13 bit12 bit11 bit10
bit15 bit14
H
CL
PEN P SBL
H
H
R/W R/W R/W
R/W R/W
H
: Initial value
bit9 bit8 bit7
AD RXE
REC TXE (SMR0 to SMR3)
W R/W R/W
Bit indicating that sending operation
TXE
0 Sending operation disabled
1
Sending operation enabled
RXE Bit indicating that receiving operation
0
Receiving operation disabled
1
Receiving operation enabled
Receiving error clear bit
REC
0 Clear FRE, ORE, PE flag.
1
The conversion is not changed and no others are affected
A/D Address/Data selection bit
0 Data frame
1 Address frame
CL Data length selection bit
7 bit
0
8 bit
1
SBL Stop bit length selection bit
0
1 bit length
1
2 bit length
Parity selection bit
P
Only enable when parity is existent (PN = 1)
Even parity
0
Odd parity
1
Parity enable bit
PEN
0 No Parity
1 With Parity
CHAPTER 21 UART
bit0
Initial value
00000100
B
483