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12.4.2
Timer Control Status Register, Lower Byte (TMCSRL0/
TMCSRL1)
The lower seven bits of the timer control status registers (TMCSR0/TMCSR1) are used
to set operating conditions for the 16-bit reload timer, enable and disable operation,
control interrupts, and check the status.
■ Timer Control Status Register, Lower Byte (TMCSRL0/TMCSRL1)
Figure 12.4-3 Timer Control Status Register, Lower Byte (TMCSRL0/TMCSRL1)
bit
15
Address
(TMCSR:H)
TMCSRL0
000082
H
TMCSRL1
000086
H
R/W: Read/write
: Initial value
* : See Section 12.4.1, "Timer control status register, upper byte", for MOD0 (bit 7)
8
7
6
5
4
3
MOD0* OUTE OUTL RELD INTE
R/W
R/W
R/W
R/W
R/W
CHAPTER 12 16-BIT RELOAD TIMER
2
1
0
Initial value
UF
CNTE TRG
00000000
R/W
R/W
R/W
Software trigger bit
TRG
During writing
0
No effect
1
After reloading, counting starts.
Count enable bit
CNTE
0
Counting stopped
1
Counting enabled (wait for the start trigger)
Underflow interrupt request flag bit
UF
During reading
0
Without counter underflow
1
With counter underflow
No effect
INTE
Underflow interrupt enable bit
0
Disable underflow interrupt
1
Enable underflow interrupt
RELD
Reload selection bit
0
Single-shot mode
1
Reload mode
Pin output level selection bit
OUTL
In single-shot mode (RELD = 0)
0
Square wave of H during counting
1
Square wave of L during counting
Timer output enable bit
OUTE
Registers and pins corresponding to each channel
Pin functions
0
General-purpose port
1
Timer output
B
During reading
Always read "0"
During writing
This bit is cleared.
In reload mode (RELD = 1)
Toggle output of L when counting is started.
Toggle output of H when counting is started.
TMCSR0
TMCSR1
P16
P21
TO0
TO1
239
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