Counter Control Register L0/1 (Ccrl0/1) - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER

13.2.3 Counter control register L0/1 (CCRL0/1)

This section describes the configuration and explains the function of counter control
register L0/1 (CCRL0/1).
I Counter control register L0/1 (CCRL0/1)
The bit configuration of counter control register L0/1 (CCRL0/1) is shown below.
Figure 13.2-4 Bit configuration of counter control register L0/1 (CCRL0/1)
Bit
CCRL0
Address: 00006C
CCRL1
Address: 000070
Counter control register L0/1(CCRL0/1) consists of bits that have the functions explained below.
[Bit 7] UDMS (up/down counting mode selection)
This bit is used to control the up/down counting at the falling edge of the BIN pin in the phase
difference counter mode at frequency multiplied by 2.
It is initialized to "0" by a reset. Read and write operations are possible.
UDMS
0
1
If this bit is rewritten after its start, the count value is not assured.
[Bit 6] CTUT (counter write)
This bit is used for transfers from RCR to UDCR.
If this bit is set to "1", data is transferred from RCR to UDCR.
Writing "0" has no effect.
[Bit 5] UCRE (UDCR clear enable)
This bit is used to control UDCR clear caused by compare.
This does not affect the UDCR clear function (such as caused by the ZIN pin setting) other
than clear because of compare generation.
UCRE
0
1
258
7 6 5
H UDMS CTUT UCRE RLDE UDCC CGSC CGE1 CGE0
R/W W R/W R/W
H
Decremented if the AIN pin value detected at the falling edge of the BIN pin is
"H" (initial value)
Incremented if AIN pin value detected at the BIN pin is "L" (initial value)
Decremented if the AIN pin value detected at the falling edge of the BIN pin is "L"
Incremented if the AIN pin value detected at the falling edge of the BIN pin is "H"
Counter clear caused by compare
Counter clear prohibit (initial value)
Counter clear permit
4 3 2 1
W R/W R/W R/W
Operation
0 Initial value
0X00X000
B