Data Bus Requirements For Read Cycles - Motorola MC68030 User Manual

Enhanced 32-811 microprocessor

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Data Bus Requirements for Read Cycles

Long-Word Port

External Oata Bytes

External Oata Bytes Required

031:024023:016 015:08

NOTE: The bytes labeled as Nn (Next n) and PRn (Previous n) are only required to be valid for cachable read cycles. They

can be interpreted as don't cares for noncachable read cycles.

Table 7-5 lists the combination$ of SIZO, SIZ1, AO, and A 1 and the corre-

sponding pattern of the data transfer for write cycles from the internal mul-

tiplexer of the MC68030 to the external data bus.

Figure 7-5 shows the transfer of a long-word operand to a word port. In the

first bus cycle, the MC68030 places the four operand bytes on the external

bus. Since the address is long-word aligned in this example, the multiplexer

follows the pattern in the entry of Table 7-5 corresponding to

SIZO_SIZ1_AO_A 1

0000. The port latches the data on bits 016-031 of the

data bus, asserts OSACK1 (OSACKO remains negated), and the processor

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