Register Descriptions - Motorola MPC8260 PowerQUICC II User Manual

Clock
External
Data Bus
(32 msb)
PSDVAL
Internal
Data Bus
(32 msb)
Internal
Data Bus
(32 lsb)
TA
Figure 10-5. Partial Data Valid for 32-Bit Port Size Memory, Double-Word Transfer

10.3 Register Descriptions

Table 10-2 lists registers used to control the 60x bus memory controller.
Table 10-2. 60x Bus Memory Controller Registers
Abbreviation
BR0ÐBR11
OR0ÐOR11]
PSDMR
LSDMR
MAMR
MBMR
MCMR
MDR
MAR
MPTPR
PURT
PSRT
LURT
LSRT
TESCRx
LTESCRx
MOTOROLA
Upper 4 bytes
Name
Base register banks 0Ð11
Option register banks 0Ð11
60x bus SDRAM machine mode register
Local bus SDRAM machine mode register
UPMA mode register
UPMB mode register
UPMC mode register
Memory data register
Memory address register
Memory refresh timer prescaler register
60x bus assigned UPM refresh timer
60x bus assigned SDRAM refresh timer
Local bus assigned UPM refresh timer
Local bus assigned SDRAM refresh timer
60x bus error status and control registers
Local bus error status and control regs
Chapter 10. Memory Controller
Part III. The Hardware Interface
Lower 4 bytes
Upper 4 bytes
Lower 4 bytes
Reference
Section 10.3.1
Section 10.3.2
Section 10.3.3
Section 10.3.4
Section 10.3.5
Section 10.3.6
Section 10.3.7
Section 10.3.12
Section 10.3.8
Section 10.3.10
Section 10.3.9
Section 10.3.11
Section 10.3.13
Section 10.3.14
10-13