16-Bit Destinations; Special Instruction Types - Motorola DSP56800 Manual

3.6.5

16-Bit Destinations

Some arithmetic instructions can generate a result for a 36-bit accumulator or a 16-bit destination such as a
register or memory location. When condition codes for a 16-bit destination are being generated, the CC bit
is ignored and condition codes are generated using the 16 bits of the result. Instructions in this category are
ADD, CMP, SUB, DECW, INCW, MAC, MACR, MPY, MPYR, ASR, and ASL.
The condition codes for 16-bit destinations are computed as follows:
• N is set if bit 15 of the result is set.
• Z is set if bits 15–0 of the result are all cleared.
• V is set if overflow has occurred in the 16-bit result.
• C is set if a carry (borrow) has occurred out of bit 15 of the result.
Other instructions only generate results for a 16-bit destination such as the logical instructions. When
condition codes are being generated for this case, the CC bit is ignored and condition codes are generated
using the 16 bits of the result. Instructions in this category are AND, EOR, LSL, LSR, NOT, OR, ROL,
and ROR. The rules for condition code generation are presented for the cases where the destination is a
16-bit register or 16 bits of a 36-bit accumulator.
The condition codes for logical instructions with 16-bit registers as destinations are computed as follows:
• N is set if bit 15 of the corresponding register is set.
• Z is set if bits 15–0 of the corresponding register are all cleared.
• V is always cleared.
• C—Computation dependent on instruction.
The condition codes for logical instructions with 36-bit accumulators as destinations are computed as
follows:
• N is set if bit 31 of the corresponding accumulator is set.
• Z is set if bits 31–16 of the corresponding accumulator are all cleared.
• V is always cleared.
• C—Computation dependent on instruction.
3.6.6

Special Instruction Types

Some instructions do not follow the preceding rules for condition code generation, and must be considered
separately. Examples of instructions in this category are the logical and bit-field instructions (ANDC,
EORC, NOTC, ORC, BFCHG, BFCLR, BFSET, BFTSTL, BFTSTH, BRCLR, and BRSET), the CLR
instruction, the IMPY(16) instruction, the multi-bit shifting instructions (ASLL, ASRR, LSLL, LSRR,
ASRAC, and LSRAC), and the DIV instruction.
The bit-field instructions only affect the C and the L bits. The CLR instruction only generates condition
codes when clearing an accumulator. The condition codes are not modified when clearing any other
register. Some of the condition codes are not defined after executing the IMPY(16) and multi-bit shifting
instructions. The DIV instruction only affects a subset of all the condition codes. See Appendix A.4,
"Condition Code Computation," on page A-6 for details on the condition code computation for each of
these instructions.
Data Arithmetic Logic Unit
Condition Code Generation
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