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DRAM Controller Operation
7.2.7
Data Retention During Reset
DRAM needs to retain data during reset, whether it is an external reset or an internal watchdog reset. The
DRAM controller itself has a special design to support this feature. Figure 7-3 illustrates the timing for
data retention.
32 kHz
External
RESET
(Hardware reset)
Internal
RESET
DRAM
Refresh
15.6 µs
CPCRESET
DRAM Reset
Port (CSCx, CSDx) Reset
System
Clock
Sleep with No SYSCLK
7-10
Figure 7-3. Data Retention for the Reset Cycle
MC68VZ328 User's Manual
DRAM Sync. with
System Clock
Reprogram
DRAM Controller,
Chip-Selects
I/O Port
(CSCx,CSDx),
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