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MPC823e Instruction Set—eieio
B-58
a cache management instruction, or implicitly by the cache
coherency mechanism). The eieio instruction does not affect
the order of accesses in one set with respect to accesses in
the other set.
The eieio instruction may complete before memory accesses
caused by instructions preceding the eieio instruction have been
performed with respect to main memory or coherent memory as
appropriate.
The eieio instruction is intended for use in managing shared
data structures, in accessing memory-mapped I/O, and in
preventing load/store combining operations in main memory. For
the first use, the shared data structure and the lock that protects
it must be altered only by stores that are in the same set (1 or 2;
see previous discussion). For the second use, eieio can be
thought of as placing a barrier into the stream of memory
accesses issued by a processor, such that any given memory
access appears to be on the same side of the barrier to both the
processor and the I/O device. Because the processor performs
store operations in order to memory that is designated as both
caching-inhibited and guarded, the eieio instruction is needed
for such memory only when loads must be ordered with respect
to stores or with respect to other loads.
Note that the eieio instruction does not connect hardware
considerations to it, such as multiprocessor implementations
that send an eieio address-only broadcast (useful in some
designs). For example, if a design has an external buffer that
reorders loads and stores for better bus efficiency, the eieio
broadcast signals to that buffer that previous loads/stores
(marked caching-inhibited, guarded, or write-through required)
must complete before any following loads/stores (marked
caching-inhibited, guarded, or write-through required).
Other registers altered:
None
POWERPC ARCHITECTURE
LEVEL
VEA
MPC823e REFERENCE MANUAL
SUPERVISOR
OPTIONAL
LEVEL
MOTOROLA
FORM
X
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