Motorola MPC823e Reference Manual page 1198

MPC823e Instruction Set—dcbf
dcbf
AssemblerSyntax
BIT 0 1 2
FIELD 31
BIT 16 17 18
FIELD B
Definition
Operation
Description
B-40
dcbf rA,rB
3 4 5 6 7
00000
19 20 21 22 23
Data Cache Block Flush
EA is the sum (rA|0) + (rB).
The dcbf instruction invalidates the block in the data cache
addressed by EA, copying the block to memory first, if there is
any dirty data in it. If the processor is a multiprocessor
implementation and the block is marked coherency-required, the
processor will, if necessary, send an address-only broadcast to
other processors. The broadcast of the dcbf instruction causes
another processor to copy the block to memory, if it has dirty
data, and then invalidate the block from the cache.
The action taken depends on the memory mode associated with
the block containing the byte addressed by EA and on the state
of that block. The list below describes the action taken for the
various states of the memory coherency attribute (M bit).
• Coherency required
Unmodified block—Invalidates copies of the block in the
data caches of all processors.
Modified block—Copies the block to memory. Invalidates
copies of the block in the data caches of all processors.
Absent block—If modified copies of the block are in the
data caches of other processors, causes them to be
copied to memory and invalidated in those data caches.
If unmodified copies are in the data caches of other
processors, causes those copies to be invalidated in
those data caches.
• Coherency not required
Unmodified block—Invalidates the block in the
processor's data cache.
MPC823e REFERENCE MANUAL
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86
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A
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MOTOROLA