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MPC823e Instruction Set—isync
isync
BIT
0
1
2
FIELD
19
BIT
16
17
18
FIELD
00000
Definition
Description
B-64
3
4
5
6
7
00000
19
20
21
22
23
Instruction Synchronize
The isync instruction provides an ordering function for the
effects of all instructions executed by a processor. Executing an
isync instruction ensures that all instructions preceding the the
isync instruction have completed before the isync instruction
completes, except that memory accesses caused by those
instructions need not have been performed with respect to other
processors and mechanisms. It also ensures that no subsequent
instructions are initiated by the processor until after the isync
instruction completes. Finally, it causes the processor to discard
any prefetched instructions, with the effect that subsequent
instructions will be fetched and executed in the context
established by the instructions preceding the isync instruction.
The isync instruction has no effect on the other processors or on
their caches. This instruction is context synchronizing.
Context synchronization is necessary after certain code
sequences that perform complex operations within the
processor. These code sequences are usually operating system
tasks that involve memory management. For example, if an
instruction "A" changes the memory translation rules in the
memory management unit (MMU) , the isync instruction must be
executed so that the instructions following instruction "A" will be
discarded from the pipeline and refetched according to the new
translation rules. This instruction is context synchronizing.
Other registers altered:
None
POWERPC ARCHITECTURE
LEVEL
VEA
MPC823e REFERENCE MANUAL
8
9
10
11
12
00000
24
25
26
27
28
150
SUPERVISOR
OPTIONAL
LEVEL
13
14
15
29
30
31
0
FORM
XL
MOTOROLA
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