Motorola MPC823e Reference Manual page 1208

MPC823e Instruction Set—divw
B-50
Other registers altered:
Condition Register (CR0 field):
Affected: LT, GT, EQ, SO (if Rc = 1)
XER:
Affected: SO, OV (if OE = 1)
The setting of the affected bits in the XER is
mode-independent, and reflects overflow of the 32-bit
result.
POWERPC ARCHITECTURE
LEVEL
UISA
MPC823e REFERENCE MANUAL
SUPERVISOR OPTIONAL
LEVEL
MOTOROLA
FORM
XO