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dcbt
Assembler Syntax
BIT
0
1
2
FIELD
31
BIT
16
17
18
FIELD
B
Definition
Operation
Description
MOTOROLA
dcbt
rA,rB
3
4
5
6
7
00000
19
20
21
22
23
Data Cache Block Touch
EA is the sum ( r A|0) + ( r B).
This instruction is a hint that performance will probably be
improved if the block containing the byte addressed by EA is
fetched into the data cache, because the program will probably
soon load from the addressed byte. The hint is ignored if the
block is caching-inhibited. Executing dcbt does not cause the
system alignment error handler to be invoked.
This instruction may be treated as a load from the addressed
byte with respect to address translation, memory protection, and
reference and change recording, except that no exception
occurs in the case of a translation fault or protection violation.
The program uses the dcbt instruction to request a cache block
fetch before it is actually needed by the program. The program
can later execute load instructions to put data into registers.
However, the processor is not obliged to load the addressed
block into the data cache.
Other registers altered:
None
POWERPC ARCHITECTURE
LEVEL
VEA
MPC823e REFERENCE MANUAL
MPC823e Instruction Set—dcbt
8
9
10
11
12
24
25
26
27
28
278
SUPERVISOR
OPTIONAL
LEVEL
13
14
15
A
29
30
31
0
FORM
X
B-45
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