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lwbrx
Assembler Syntax
BIT
0
1
2
FIELD
31
BIT
16
17
18
FIELD
B
Definition
Operation
Description
MOTOROLA
lwbrx
rD,rA,rB
3
4
5
6
7
19
20
21
22
23
Load Word Byte-Reverse Indexed
if rA = 0 then b ← 0
else b ← (rA)
EA ← b + (rB)
rD ← MEM(EA + 3, 1) || MEM(EA + 2, 1) || MEM(EA + 1, 1) ||
MEM(EA, 1)
EA is the sum (rA|0) + rB. Bits 0–7 of the word in memory
addressed by EA are loaded into the low-order 8 bits of rD. Bits
8–15 of the word in memory addressed by EA are loaded into the
subsequent low-order 8 bits of rD. Bits 16–23 of the word in
memory addressed by EA are loaded into the subsequent
low-order eight bits of rD. Bits 24–31 of the word in memory
addressed by EA are loaded into the subsequent low-order 8 bits
of rD. The MPC823e may run the lwbrx instructions with greater
latency than other types of load instructions.
Other registers altered:
None
POWERPC ARCHITECTURE
LEVEL
UISA
MPC823e REFERENCE MANUAL
MPC823e Instruction Set—lwbrx
8
9
10
11
12
D
24
25
26
27
28
534
SUPERVISOR
OPTIONAL
LEVEL
13
14
15
A
29
30
31
0
FORM
X
B-85
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