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MPC823e Instruction Set—icbi
icbi
Assembler Syntax
BIT
0
1
2
FIELD
31
BIT
16
17
18
FIELD
B
Definition
Description
B-62
icbi
rA,rB
3
4
5
6
7
00000
19
20
21
22
23
Instruction Cache Block Invalidate
EA is the sum (rA|0) + (rB).
If the block containing the byte addressed by EA is in coherency-
required mode, and a block containing the byte addressed by EA
is in the instruction cache of any processor, the block is made
invalid in all such instruction caches, so that subsequent
references cause the block to be refetched.
If the block containing the byte addressed by EA is in coherency-
not-required mode, and a block containing the byte addressed
by EA is in the instruction cache of this processor, the block is
made invalid in that instruction cache, so that subsequent
references cause the block to be refetched. The function of this
instruction is independent of the write-through, write-back, and
caching-inhibited/allowed modes of the block containing the byte
addressed by EA.
This instruction is treated as a load from the addressed byte with
respect to address translation and memory protection. It may
also be treated as a load for referenced and changed bit
recording except that referenced and changed bit recording may
not occur. Implementations with a combined data and instruction
cache treat the icbi instruction as a no-op, except that they may
invalidate the target block in the instruction caches of other
processors if the block is in coherency-required mode.
The icbi instruction invalidates the block at EA (rA|0 + rB). If the
processor is a multiprocessor implementation and the block is
marked coherency-required, the processor will send an address
only broadcast to other processors causing those processors to
invalidate the block from their instruction caches.
MPC823e REFERENCE MANUAL
8
9
10
11
12
24
25
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28
982
13
14
15
A
29
30
31
0
MOTOROLA
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