Data Address Register (Dar); Time Base Facility (Tb) - Oea - Motorola MPC533 Reference Manual

3.9.3

Data Address Register (DAR)

After an alignment exception, the DAR, SPR 19, is set to the effective address of a load or
store element.
MSB 1 2 3 4
0
Field
Reset
Addr
3.9.4 Time Base Facility (TB) — OEA
As described in Section 3.8, "VEA Register Set — Time Base (TB)," the time base (TB)
provides a 64-bit incrementing counter. Whereas the VEA defines user-level, read-only
access to the TB, the OEA defines supervisor-level, write access. Writing to the TB, SPR
284 (TBL) and 285 (TBU), is reserved for supervisor-level applications such as operating
systems and bootstrap routines.
MSB
0
Field
Reset
Addr
Table 3-14. Time Base Field (Write Only) Bit Descriptions
Bits Name
0:31 TBU Time Base (Upper). The high-order 32 bits of the time base
32:63 TBL Time Base (Lower). The low-order 32 bits of the time base
The TB can be written to at the supervisor-level only. The mttbl and mttbu simplified
mnemonics write the lower and upper halves of the TB, respectively. The mtspr, mttbl, and
mttbu instructions treat TBL and TBU as separate 32-bit registers; setting one leaves the
other unchanged. It is not possible to write the entire 64-bit time base in a single instruction.
For information about reading the time base, refer to Section 3.8, "VEA Register Set —
Time Base (TB)."
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 LSB
Figure 3-14. Data Address Register (DAR)
TBU
Figure 3-15. Time Base (Write Only)
Chapter 3. Central Processing Unit
Data Address
Unchanged
SPR 19
31 32
Unaffected
SPR 285, SPR 284
Description
OEA Register Set
LSB
63
TBL
3-25
31