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2.6 Operand Addressing Capabilities
M•CORE accesses all memory operands through load and store instructions, trans-
ferring data between the general-purpose registers and memory. Register-plus-four-
bit scaled displacement addressing mode is used for the load and store instructions
to address byte, halfword, or word (32-bit) data.
Load and store multiple instructions allow a subset of the 16 GPRs to be transferred
to or from a base address pointed to by register R0 (the default stack pointer by con-
vention).
Load and store register quadrant instructions use register indirect addressing to
transfer a register quadrant to or from memory.
2.7 Instruction Set Overview
The instruction set is tailored to support high-level languages and is optimized for
those instructions most commonly executed. A standard set of arithmetic and logical
instructions is provided, as well as instruction support for bit operations, byte extrac-
tion, data movement, control flow modification, and a small set of conditionally exe-
cuted instructions which can be useful in eliminating short conditional branches.
Table 2-1 is an alphabetized listing of the M•CORE instruction set. Refer to the
M•CORE Reference Manual (MCORERM/AD) for more details on instruction opera-
tion.
Mnemonic
ABS
ADDC
ADDI
ADDU
AND
ANDI
ANDN
ASR
ASRC
BCLRI
BF
BGENI
BGENR
BKPT
BMASKI
BR
BREV
BSETI
BSR
BT
BTSTI
MOTOROLA
2-6
Freescale Semiconductor, Inc.
Table 2-1 M•CORE Instruction Set
Absolute Value
Add with C Bit
Add Immediate
Add Unsigned
Logical AND
Logical AND Immediate
AND NOT
Arithmetic Shift Right
Arithmetic Shift Right, Update C Bit
Bit Clear Immediate
Branch on Condition False
Bit Generate Immediate
Bit Generate Register
Breakpoint
Bit Mask Immediate
Branch
Bit Reverse
Bit Set Immediate
Branch to Subroutine
Branch on Condition True
Bit Test Immediate
INTEGER CPU
For More Information On This Product,
Go to: www.freescale.com
Description
REFERENCE MANUAL
MMC2001
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