3.2 Hardware Design - Renesas H8SX series User Manual

Direct Drive LCD Design Guide

3.2 Hardware Design

Below is a block diagram of a LCD system which uses Flash and SRAM for respectively storing and
buffering the images to be displayed.
The following table describes the TPU channels and pins used for direct drive. Note that the TPU
synchronization capability is used to create a common time base between the HDEN, HSYNC and
VSYNC pins.
Signal
DOTCLK
DOTPER
HDEN
HDEN2
HSYNC
VSYNC
HPER
Note 1: Dot Clock Logic
Note 2: Touch Screen
TPU Channel Requirements
Output using PWM 1 Mode
TGR to set period of DOTCLK
Output using PWM 2 Mode
TGR for PWM 2 Mode
Output using PWM 1 Mode
Output using PWM 1 Mode
TGR to set horizontal period
Figure 9 Block Diagram
14
Suggested
Channel
1, 2, 4 or 5
same as DOTCLK
1, 2, 4 or 5
same as HDEN
0 or 3
same as HSYNC
same as HSYNC