Hdl Code Examples: Transceiver Bypassing Of 8B/10B Encoding; Crc Operation; Crc Generation; Figure 3-13: 4-Byte Serial Structure - Xilinx RocketIO User Manual

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The serial data bit sequence is dependent on the width of the parallel data. The most
significant byte is always sent first regardless of the whether 1-byte, 2-byte, or 4-byte paths
are used. The least significant byte is always last.
data corresponds to each byte of the parallel data. TXDATA [31:24] is serialized and sent
out first followed by TXDATA [23:16], TXDATA [15:8], and finally TXDATA [7:0]. The 2-
byte path transmits TXDATA [15:8] and then TXDATA [7:0].

HDL Code Examples: Transceiver Bypassing of 8B/10B Encoding

8B/10B encoding can be bypassed by the transceiver. The TX8B10BBYPASS is set to 1111;
the RXDECODE attribute is set to "FALSE" to create the extra two bits needed for a 10-bit
data bus; and TXCHARDISPMODE, TXCHARDISPVAL, RXCHARISK, and RXRUNDISP
are added to the 8-bit data bus.
Availability for download of code examples with 8B/10B bypassing is planned for a later
date.

CRC Operation

Cyclic Redundancy Check (CRC) is a procedure to detect errors in the received data. There
are four possible CRC modes, USER_MODE, ETHERNET, INFINIBAND, and
FIBRE_CHAN. These are only modifiable for the GT_XAUI and GT_CUSTOM. Each mode
has a start-of-packet (SOP) and end-of-packet (EOP) setting to determine where to start
and end the CRC monitoring. USER_MODE allows the user to define the SOP and EOP by
setting the CRC_START_OF_PKT and CRC_END_OF_PKT to one of the valid
K-characters
Whenever these attributes are set to TRUE, CRC is used. A CRC error can be "forced" with
the use of TXFORCECRCERR. This causes TX_CRC_FORCE_VALUE to be XORed with
the computed CRC, to test the CRC error logic.

CRC Generation

RocketIO transceivers support a 32-bit invariant CRC (fixed 32-bit polynomial shown
below) for Gigabit Ethernet, Fibre Channel, Infiniband, and user-defined modes.
The CRC recognizes the SOP (Start of Packet), EOP (End of Packet), and other packet
features to identify the beginning and end of data. These SOP and EOP are defined by the
mode, except in the case where CRC_MODE is USER_DEFINED. The user-defined mode
uses CRC_START_OF_PKT and CRC_END_OF_PKT to define SOP and EOP.
70
H 3 − A 3 H 2 − A 2
TXDATA 31:24 TXDATA 23:16
a 3 − j 3 a 2 − j 2
LSB 3 LSB 2
1 st Sent 2 nd Sent
Encoded Encoded

Figure 3-13: 4-Byte Serial Structure

(Table 3-14). The CRC is controlled by RX_CRC_USE and TX_CRC_USE.
32 26 23 22 16
x + x + x + x + x +
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Chapter 3: Digital Design Considerations
Figure 3-13 shows a case when the serial
H 1 − A 1
TXDATA 15:8
8B/10B
a 1 − j 1
LSB 1
3 rd Sent
Encoded
12 11 10 8 7
x + x + x + x + x + x
UG024 (v1.5) October 16, 2002
RocketIO™ Transceiver User Guide
H 0 − A 0
TXDATA 7:0
a 0 − j 0
LSB 0
4 th Sent
Encoded
U024_11_020802
5 4 2 1
1
+ x + x + x +