ST STM32L4+ Series Reference Manual page 2262

Debug support (DBG)
The packets emitted by the ITM are output to the TPIU (trace port interface unit). The
formatter of the TPIU adds some extra packets (refer to TPIU) and then output the complete
packets sequence to the debugger host.
The bit TRCEN of the debug exception and monitor control register must be enabled before
you program or use the ITM.
57.14.2 Time stamp packets, synchronization and overflow packets
Time stamp packets encode time stamp information, generic control and synchronization. It
uses a 21-bit timestamp counter (with possible prescalers) which is reset at each time
stamp packet emission. This counter can be either clocked by the CPU clock or the SWV
clock.
A synchronization packet consists of 6 bytes equal to 0x80_00_00_00_00_00 which is
emitted to the TPIU as 00 00 00 00 00 80 (LSB emitted first).
A synchronization packet is a timestamp packet control. It is emitted at each DWT trigger.
For this, the DWT must be configured to trigger the ITM: the bit CYCCNTENA (bit0) of the
DWT control register must be set. In addition, the bit2 (SYNCENA) of the ITM trace control
register must be set.
Note: If the SYNENA bit is not set, the DWT generates synchronization triggers to the TPIU which
sends only TPIU synchronization packets and not ITM synchronization packets.
An overflow packet consists is a special timestamp packets which indicates that data has
been written but the FIFO was full.
Address
@E0000FB0 ITM lock access
@E0000E80
2262/2301
Table 434. Main ITM registers
Register
Write 0xC5AC CE55 to unlock write access to the other ITM
registers
Bits 31-24 = always 0
Bits 23 = busy
Bits 22-16 = 7-bits ATB ID which identifies the source of the
trace data
Bits 15-10 = always 0
Bits 9:8 = TSPrescale = time stamp prescaler
Bits 7-5 = reserved
ITM trace control
Bit 4 = SWOENA = enable SWV behavior (to clock the
timestamp counter by the SWV clock)
Bit 3 = DWTENA: enable the DWT Stimulus
Bit 2 = SYNCENA: this bit must be to 1 to enable the DWT to
generate synchronization triggers so that the TPIU can then
emit the synchronization packets
Bit 1 = TSENA (timestamp enable)
Bit 0 = ITMENA: global enable bit of the ITM
RM0432 Rev 6
Details
RM0432