ST STM32L4+ Series Reference Manual page 2257

RM0432
Bit
0..2
The ACK response must be followed by a turnaround time only if it is a READ transaction or
if a WAIT or FAULT acknowledge has been received.
Bit
0..31
32
The DATA transfer must be followed by a turnaround time only if it is a READ transaction.
57.8.3 SW DP state machine (reset, idle states, ID code)
The state machine of the SW-DP has an internal ID code which identifies the SW-DP. It
follows the JEP-106 standard. This ID code is the default Arm
0x1BA0 1477 (corresponding to Cortex
Note: Note that the SW-DP state machine is inactive until the target reads this ID code.
•
The SW-DP state machine is in RESET STATE either after power-on reset, or after the
DP has switched from JTAG to SWD or after the line is high for more than 50 cycles
• The SW-DP state machine is in IDLE STATE if the line is low for at least two cycles
after RESET state.
•
After RESET state, it is mandatory to first enter into an IDLE state AND to perform a
READ access of the SW-DP ID CODE register. Otherwise, the target issues a FAULT
acknowledge response on another transactions.
Further details of the SW-DP state machine can be found in the Arm
Components Technical Reference Manual.
57.8.4 DP and AP read/write accesses
•
Read accesses to the DP are not posted: the target response can be immediate (if
ACK=OK) or can be delayed (if ACK=WAIT).
•
Read accesses to the AP are posted. This means that the result of the access is
returned on the next transfer. If the next access to be done is NOT an AP access, then
the DP-RDBUFF register must be read to obtain the result.
The READOK flag of the DP-CTRL/STAT register is updated on every AP read access
or RDBUFF read request to know if the AP read access was successful.
•
The SW-DP implements a write buffer (for both DP or AP writes), that enables it to
accept a write operation even when other transactions are still outstanding. If the write
buffer is full, the target acknowledge response is "WAIT". With the exception of
Table 429. ACK response (3 bits)
Name
001: FAULT
ACK 010: WAIT
100: OK
Table 430. DATA transfer (33 bits)
Name
WDATA or RDATA Write or Read data
Parity Single parity of the 32 data bits
RM0432 Rev 6
Description
Description
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-M4 r0p1).
Debug support (DBG)
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one and is set to
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CoreSight
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