ST STM32L4+ Series Reference Manual page 2270

Debug support (DBG)
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
DBG_T
Res. Res. IM8_S Res.
TOP
rw
Bits 31:19 Reserved, must be kept at reset value.
Bit 18 DBG_TIM17_STOP: TIM17 counter stopped when core is halted
0: The clock of the TIM17 counter is fed even if the core is halted
1: The clock of the TIM17 counter is stopped when the core is halted
Bit 17 DBG_TIM16_STOP: TIM16 counter stopped when core is halted
0: The clock of the TIM16 counter is fed even if the core is halted
1: The clock of the TIM16 counter is stopped when the core is halted
Bit 16 DBG_TIM15_STOP: TIM15 counter stopped when core is halted
0: The clock of the TIM15 counter is fed even if the core is halted
1: The clock of the TIM15 counter is stopped when the core is halted
Bits 15:14 Reserved, must be kept at reset value.
Bit 13 DBG_TIM8_STOP: TIM8 counter stopped when core is halted
0: The clock of the TIM8 counter is fed even if the core is halted
1: The clock of the TIM8 counter is stopped when the core is halted
Bit 12 Reserved, must be kept at reset value.
Bit 11 DBG_TIM1_STOP: TIM1 counter stopped when core is halted
0: The clock of the TIM1 counter is fed even if the core is halted
1: The clock of the TIM1 counter is stopped when the core is halted
Bits 10:0 Reserved, must be kept at reset value.
2270/2301
27 26 25 24
Res. Res. Res. Res.
11 10 9 8
DBG_
TIM1_ Res. Res. Res.
STOP
rw
RM0432 Rev 6
23 22 21 20
Res. Res. Res. Res.
7 6 5 4
Res. Res. Res. Res.
RM0432
19 18 17
DBG_TI DBG_TI DBG_TI
Res. M17_ST M16_ST M15_ST
OP OP
rw rw
3 2 1
Res. Res. Res.
16
OP
rw
0
Res.