ST STM32L4+ Series Reference Manual page 2282

Revision history
59 Revision history
Date
13-Oct-2017
05-Feb-2018
2282/2301
Table 441. Document revision history
Revision
1 Initial release.
Added:
– Section 3.7.17: Flash configuration register (FLASH_CFGR)
– Section 12.6.7: DMAMUX size identification register
(DMAMUX_SIDR)
– Section 12.6.8: DMAMUX IP identification register
(DMAMUX_IPIDR)
– Section 12.6.9: DMAMUX version register (DMAMUX_VERR)
– Section 12.6.10: DMAMUX hardware configuration 1 register
(DMAMUX_HWCFGR1)
– Section 12.6.11: DMAMUX hardware configuration 2 register
(DMAMUX_HWCFGR2)
– CS boundary, refresh and communication regulation features
Section 19.2.4: Common functionality between the regular-
command mode and HyperBus™
– Status flag polling mode configuration
2
OCTOSPI regular-command mode configuration
– Section 19.4.7: OCTOSPI reconfiguration or deactivation
– Section 19.6.5: OCTOSPI device configuration register 4
(OCTOSPI_DCR4)
– Section 41.4.14: Timer counter reset
– Section 56.4.2: OTG_FS pin and internal signals
– Table 415: Compatibility of STM32 low power modes with the
OTG
Figure 622: Updating OTG_HFIR dynamically (RLDCTRL = 1)
Deleted:
– Figure CS high time and clocked CS high timer
– OCTOSPI registers: OCTOSPI HW configuration register,
(OCTOSPI_HWCFGR), OCTOSPI version register
(OCTOSPI_VER), OCTOSPI identification (OCTOSPI_ID),
OCTOSPI HW magic ID (OCTOSPI_MID)
RM0432 Rev 6
Changes
on Section 19.4.3:
RM0432
on